The present invention relates generally to the field of receiving of data input to semiconductor integrated circuits, and more specifically, to receiver circuits to transfer external signals to internal circuits in the integrated circuit chips.
The transmission of data between integrated circuits such as high-speed digital circuits may be broken down to a timing budget in the overall system architecture. When data is received by an integrated circuit, it is typically buffered and latched and only after buffering and latching the data is considered successfully captured. In high-speed digital circuits, the faster the data can be latched, the further data can be transmitted. During input operations in digital circuits, data enters the integrated circuit through receiver circuits and the data signal is buffered and fed to a latch. The data is captured by the latch on an edge or level of a system clock. To optimize this process, various input circuit implementations have been devised to minimize the delay through the buffer and setup time of the latch. For instance, design and placement of input buffer and latch circuit components may minimize this time, but currently resulting in some portion of the overall timing budget.
FIG. 1 shows circuit architecture of a receiver circuit embedded in a semiconductor integrated circuit such as a synchronous DRAM to receive an external signal and to convert the external signal into an internal signal with a CMOS digital level, including a pre-amplifier 10, a first amplifier 30, and a second amplifier 50.
The pre-amplifier 10 is formed of resistors 11 and 12, a pair of differential input transistors 13 and 14, and a control transistor 15. Gates of the differential input transistors 13 and 14 are coupled to a data signal D and a reference voltage Vref, respectively. The differential input transistors 13 and 14 become conductive when a bias voltage Vbias applied to a gate of the control transistor 15 is charged up to a high level (e.g., 0.8V) enough to turn the control transistor on. On an sufficiently high-leveled Vbias, voltages at drain nodes of the differential input transistors 13 and 14 are output as differential signals PQB and PQ, respectively, according to a voltage difference between the data signal D and the reference voltage Vref.
In the first amplifier 30, including a pair of precharge transistors 31 and 32, a pair of constant-current transistors 33 and 34, a pair of equalizing transistors 35 and 36, a pair of voltage detection transistors 37 and 38, a pair of differential input transistors 39 and 40, an a pair of control transistors 41 and 42, differential signals IQ and IQB are made from voltages at drain nodes of the voltage detection transistors while a clock signal CLK is at a high level after receiving the differential signals PQB and PQ from the pre-amplifier 10. The second amplifier 50, including a pair of precharge transistors 53 and 54, a pair of constant-current transistors 55 and 56, a pair of inverters 57 and 58, a pair of voltage detection transistors 59 and 60, and a pair of differential input transistors 61 and 62, provides amplified differential signals Q and QB into internal circuits of an integrated circuit, which are generated at drain nodes of the voltage detection transistors 59 and 60 after amplifying the signals IQB and IQ supplied from the first amplifier 30.
In the receiver circuit 1, an on-resistance of the differential input transistor 13 becomes larger than that of the transistor 14 when a voltage level of the data signal D is higher than the reference voltage Vref, resulting in a lower drain voltage of the transistor 13 under a drain voltage of the transistor 14. Thus, the differential signal PQB is lowered under the differential signal PQ. With PQB lower than PQ, an on-resistance of the transistor 39 becomes larger than that of the transistor 40. Thus, the drain voltage IQ of the transistor 37 goes up to a higher level over the drain voltage IQB of the transistor 38. And, with IQ higher than IQB, an on-resistance of the transistor 61 becomes smaller than that of the transistor 62, resulting in a lower drain voltage of the transistor 59 under a drain voltage of the transistor 60. As a result, the data signal D lower than the reference voltage Vref makes a voltage level of the differential output signal Q higher than that of the differential output signal QB.
When a voltage level of the data signal D is lower than the reference voltage Vref, an on-resistance of the differential input transistor 13 becomes smaller than that of the differential input transistor 14, resulting in a higher drain voltage of the transistor 13 over a drain voltage of the transistor 14. Thus, the differential signal PQB rises over the differential signal PQ. With PQB higher than PQ, an on-resistance of the transistor 39 becomes smaller than that of the transistor 40. Thus, the drain voltage IQ of the transistor 37 drops to a lower level under the drain voltage IQB of the transistor 38. And, with IQ higher than IQB, an on-resistance of the transistor 61 becomes larger than that of the transistor 62, resulting in a higher drain voltage of the transistor 59 over a drain voltage of the transistor 60. As a result, the data signal D leveled higher than the reference voltage Vref makes a voltage level of the differential output signal Q lower than that of the differential output signal QB.
In a practical implementation, the data signal D may swing in the range of 1.2Vxc2x10.4V when the reference voltage Vref is set at 1.2V.
As well known, the control transistor 15 as an NMOS transistor is saturated in the condition of:
Vdsxe2x89xa7(Vgsxe2x88x92Vth)xe2x80x83xe2x80x83Equation 1
The drain voltage Vds of the control transistor 15 may be obtained from the following if the bias voltage Vbias applied to the gate of the control transistor 15 is 0.8V and the threshold voltage Vth of the control transistor 15 is 0.4V:
Vds=0.8xe2x88x920.4xe2x88x92xcex94xe2x80x83xe2x80x83Equation 2
where xcex94 is an over-drive voltage approximately over 0.1V.
For instance, when xcex94 is 0.1V, Vds becomes 0.3V. This result is incapable of satisfying the saturation condition of Equation 1, still situating the control transistor 15 in an unstable operation state.
Decreasing the bias voltage Vbias to 0.7V from 0.8V may achieve a stabilized conductive state of the control transistor 15 because it is saturated by the condition of Vds=0.7xe2x88x920.4. However, such a decrement of the bias voltage Vbias from 0.8V to 0.7V is accompanied by an up-sizing of the control transistor, increasing a junction capacitance thereof and decreasing a common mode rejection ratio at a high frequency.
Moreover, as the pre-amplifier 10 is forced into a conductive state just in response to the bias voltage Vbias regardless of input of the data signal D, unnecessary current consumption in the receiver circuit 1 results even without a valid input of the data signal D.
The receiver circuit 1 may be modified without the pre-amplifier to eliminate the unnecessary current consumption, by directly connecting the reference voltage Vref and the data signal D to gates of the differential input transistors 39 and 40, respectively, while switches SW1xcx9cSW4 are set to be normally turned on and nodes axcx9cd are cut off.
With the cutdown architecture of the receiver circuit, the control transistors 41 and 42 are turned off when the clock signal CLK is on a low level and the drain nodes of the differential input transistors 39 and 40 are charged up to VDDxe2x88x92Vth37 (Vth37 is the threshold voltage of the transistor 37) and VDDxe2x88x92Vth38 (Vth38 is the threshold voltage of the transistor 38), respectively, through the precharge transistors 31 and 32. If the clock signal CLK goes up to a high level, the control transistors 41 and 42 are turned on and the drain nodes of the transistors 39 and 40 drops to a ground voltage (i.e., 0V).
During this process, coupling capacitances are formed between the gate and drain nodes, and the gate and source nodes, of the differential input transistors 39.
It is generally known that an integrated circuit is comprised of a multiplicity of input terminals each of which is associated with a receiver circuit as shown in FIG. 1. A sum of the coupling capacitance at the differential input transistors, under the condition in which the reference voltage Vref is applied to a number of receiver circuits, acts as noise degrading the reference voltage level when the drain node of the transistor 39 is being discharged to 0V. Such an effect is called xe2x80x9ckick-back noisexe2x80x9d. While a large enough swing width of the data signal D may not affect normal operation of a receiver circuit even with a lower reference voltage, a decreased swing width of the data signal causes difficulty in detecting a voltage difference between them in the receiver circuit.
It is thus an object of the present invention to provide a receiver circuit capable of enhancing accuracy in detecting a data signal.
It is another object of the present invention to provide a receiver circuit capable of detecting a data signal with decreased kick-back noise.
According to an aspect of the present invention, there is provided a receiver circuit converting a data signal to a pair of output signals in response to a clock signal, comprising: a first circuit for developing a voltage difference between the data signal and a reference voltage and for outputting the voltage difference from a pair of terminals, when the clock signal is in a first state; and a second circuit for generating the output signals amplified from outputs of the first circuit. In particular, the first circuit comprises: an amplifier for precharging a pair of nodes thereof when the clock signal is in a second state and for developing a voltage difference between the nodes during the first state of the clock signal; a pair of switching transistors, being connected to the nodes, respectively, whose gates are coupled to the clock signal; and a pair of input transistors, connected between the switching transistors and a ground voltage, respectively, whose gates are coupled to the reference voltage and the data signal.
In one embodiment, the switching and input transistors are NMOS transistors.
The switching transistors connect the nodes to the input transistors during the first state of the clock signal.
The first circuit further comprises a constant-current circuit for supplying a current statically to the output terminals during the first state of the clock signal. The constant-current circuit includes a pair of constant-current transistors connected between a power supply voltage and the output terminals, respectively, whose gates and drains are cross-coupled to each other
The amplifier comprises: a pair of precharge transistors of PMOS transistors, being connected between a power supply voltage and the output terminals, respectively, whose gates are coupled to the clock signal; and a pair of voltage detection transistors of NMOS transistors, being connected between the output terminals and the nodes, whose gates and drains are cross-coupled to each other.
According to another aspect of the invention, there is provided a receiver circuit converting a data signal to a pair of output signals in response to a clock signal, comprising: a first circuit for developing a voltage difference between the data signal and a reference voltage and for outputting the voltage difference from a pair of terminals, when the clock signal is in a first state; and a second circuit for generating the output signals amplified from outputs of the first circuit, in which the first circuit comprises: an amplifier for precharging a pair of nodes thereof when the clock signal is in a second state and for developing a voltage difference between the nodes during the first state of the clock signal; a pair of switching transistors, being connected to the nodes, respectively, whose gates are coupled to the clock signal; a pair of input transistors, connected between the switching transistors and a ground voltage, respectively, whose gates are coupled to the reference voltage and the data signal; and a resistor connected between the input transistors.
In still another aspect of the invention, a receiver circuit, for converting a data signal to a pair of output signals in response to a clock signal, comprises: a first circuit for developing a voltage difference between the data signal and a reference voltage and for outputting the voltage difference from a pair of terminals, when the clock signal is in a first state; and a second circuit for generating the output signals amplified from outputs of the first circuit, in which the first circuit comprises: an amplifier for precharging a pair of nodes thereof when the clock signal is in a second state and for developing a voltage difference between the nodes during the first state of the clock signal; a pair of switching transistors, being connected to the nodes, respectively, whose gates are coupled to the clock signal; a pair of input transistors, connected between the switching transistors and a ground voltage, respectively, whose gates are coupled to the reference voltage and the data signal; and a pair of discharge transistors, being connected between the input transistors, respectively, and the ground voltage, whose gates are coupled to the reference voltage and the data signal, respectively.
The first circuit may further include a delay circuit for transferring the clock signal with a predetermined delay time. The gates of the discharge transistors being coupled to a delayed clock signal provided from the delay circuit.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.